A conventional prior art TTL to ECL/CML input buffer and translator circuit is illustrated in FIG. 1. The translator circuit incorporates an ECL gate, also referred to herein as an ECL base differential gate, coupled between the high potential power rail V.sub.CC and the low potential power rail V.sub.EE. In this example the high potential power rail V.sub.CC may be at, for example, 4.5 or 5.0 volts while the low potential power rail V.sub.EE may be at 0 volts or ground potential (GND).
The ECL gate is a base differential gate with an input transistor Q4 for receiving input signals of logic high and low potential levels at its base node, and a reference transistor element Q5. A threshold signal voltage level between the logic high and low potential input signal levels is applied at the base node of the reference transistor element Q5. The emitter terminals of ECL gate transistors Q4 and Q5 are coupled together at a common emitter node coupling. A current sink provided by emitter follower current source transistor element Q6 and emitter or tail resistor R6 is coupled between the common emitter node coupling of ECL gate transistors Q4 and Q5 and the low potential power rail V.sub.EE. With the current source voltage V.sub.CS applied at the base node of current source transistor element Q6, the current sink generates the sink current or tail current through either of the alternative current paths provided by the ECL gate transistor elements Q4 and Q5. A band-gap bias generator, not shown, but available as a part of a larger ECL integrated circuit, generates the temperature compensated current source voltage level V.sub.CS.
The base node of input transistor element Q4 is coupled through input diode SD1, in this example a Schottky diode, to the TTL input, TTL IN. The TTL input receives TTL signals of typical TTL logic high and low potential levels, for example between a high of +5.0 v and a low of 0 v or ground potential. The input clamp circuit applies controlled logic high and low signal potential levels V.sub.TM, V.sub.TL at the base node of the input transistor element Q4.
The input clamp circuit is a diode stack provided by base collector shorted (BCS) transistor elements Q1, Q2 and Q3 coupled in series between the base node of input transistor element Q4 and the low potential power rail V.sub.EE. Collector resistor R2 is a biasing resistor or current sourcing resistor which forward biases BCS transistor element diodes Q2 and Q3 with current passing through R2, Q2 and Q3 from V.sub.CC to V.sub.EE. With a TTL logic high potential level signal of for example 4.5 or 5.0 volts at the TTL input, current passes from V.sub.CC through current sourcing resistor element R1 and forward biases BCS transistor element diode Q1 at the top of the diode stack. The input clamp circuit diode stack is then operative to apply the selected logic high signal potential level V.sub.TM in the range of for example, approximately 2.2 v to 2.4 v at the base node of input transistor element Q4. When a TTL logic low potential level of for example 0 v or ground potential V.sub.EE is applied at the TTL input, current from V.sub.CC through current sourcing resistor element R1 is diverted through the input diode SD1 to ground potential. The input diode SD1 applies or clamps the selected logic low signal potential level V.sub.TL, in the range of for example 0.6 v to 0.8 v at the base node of input transistor element Q4.
As alternating logic high and low signal levels V.sub.TM, V.sub.TL are applied at the base node of input transistor element Q4, a single reference voltage or threshold voltage V.sub.TM is applied at the base node of reference transistor element Q5. In the conventional TTL to ECL/CML translator circuit of FIG. 1, the threshold voltage V.sub.TM, sometimes referred to as V.sub.IN REF, is established by a threshold clamp circuit, typically a diode stack. The diode stack in this example is provided by BCS transistor element diodes Q8 and Q7, and diode SD2 coupled in series between the base node of reference transistor element Q5 and the low potential power rail V.sub.EE. In this case diode SD2 is a Schottky diode intended to match and offset the characteristics of the input diode SD1.
The diode stack SD2, Q7 and Q8 is forward biased by current passing through the diodes from biasing resistor or current sourcing resistor R5 coupled between the base node of reference transistor element Q5 and the high potential power rail V.sub.CC. The threshold clamp circuit components are selected to apply a threshold voltage level V.sub.TM at the base node of the reference transistor element Q5 of for example 1.4 v or 1.5 v, substantially intermediate between the logic high and low signal levels V.sub.TH, V.sub.IT, applied at the base node of input transistor element Q4.
The ECL differential gate transistor elements Q4 and Q5 provide alternative current paths through respective collector path swing voltage resistor elements R3 and R4 which are in turn coupled to the high potential power rail V.sub.CC. Typically the swing voltage resistor elements R3 and R4 have substantially equal resistance. The current sink provided by current sourcing transistor element Q6 and tail resistor R6 generates the ECL gate current in one of the alternative current paths through either of the swing resistor elements R3 or R4 according to the logic high or low signal potential level V.sub.TH, V.sub.TL at the base node of input transistor element Q4.
The ECL base differential gate output signals are taken from the collector nodes of the ECL gate transistor elements Q4 and Q5. The collector nodes of Q4 and Q5 are output switching nodes which provide current mode logic output signals of high and low potential through respective output buffer emitter follower transistor elements Q9 and Q10 to the ECL output ECL OUT. Two sets of complementary outputs are provided at the ECL output. The first set of complementary outputs O.sub.B (0) (false or inverting), C.sub.B (1) (true or non-inverting) is taken respectively from the emitter nodes of the emitter follower output buffer transistor elements Q9 and Q10. The second set of complementary outputs is level shifted down by a set of BCS transistor element diodes Q11 and Q12 coupled in series respectively to the emitter nodes of the emitter follower output buffer transistor elements Q9 and Q10. The second set of complementary outputs O.sub.c (0), O.sub.c (1) is taken from the emitter nodes of BCS transistor elements Q11 and Q12.
A double current sink provided by current source transistor elements Q13, Q14 and common emitter node tail resistor R7 forward biases the emitter follower output buffer transistor elements Q9 and Q10 respectively and level shifting diodes Q11 and Q12 respectively for providing the ECL output signals. The temperature compensated current source voltage level V.sub.CS generated by the on-chip band-gap bias generator is applied at the base nodes of the current source transistor elements Q13 and Q14 for generating the sink current or tail current through the respective output transistor elements.
A characteristic of stable ECL gate operation is that the voltage levels or potentials at the base nodes of the ECL differential gate transistor elements are referenced to the same power rail. In conventional ECL integrated circuits the ECL logic high and low potential levels are referenced to the high potential power rail. The voltage levels or potential levels at the base nodes of the internal ECL gate transistor elements are therefore referenced to the high potential power rail.
TTL logic high and low potential levels however are referenced to the low potential power rail or ground rail. In the case of a TTL to ECL/CML translator circuit, the TTL input signals to the input transistor element of the translator circuit ECL gate are referenced to the low potential power rail. The input clamp circuit provided by BCS transistor elements Q1, Q2 and Q3 and the input diode SD1 set the voltage levels of the logic high and low signal potential levels V.sub.TH, V.sub.TL with reference to the ground rail V.sub.EE. The threshold clamp circuit diode stack SD2, Q7 and Q8 therefore also sets the intermediate reference voltage level or threshold voltage level V.sub.TM with reference to the ground rail V.sub.EE.
In conventional ECL integrated circuits the band-gap bias generator generates the reference voltage levels for the internal ECL gates. Thus in addition to providing the temperature compensated current source voltage level V.sub.CS for operating the current sinks and current source transistor elements of the internal ECL circuits, it also generates the threshold voltage level, generally designated V.sub.BB applied to the base nodes of the reference transistor elements of each of the internal ECL gates. The reference voltage level or threshold voltage level V.sub.BB generated by the band-gap bias generator is however established with reference to the high potential power rail and therefore cannot be applied to the base node of the reference transistor element of the translator circuit ECL gate. It is for this reason that a separate threshold clamp circuit is provided as illustrated in FIG. 1 to establish the threshold voltage level V.sub.TH with reference to the low potential or ground potential power rail. In this manner the voltage levels at the base nodes of the input and reference transistor elements of the translator circuit ECL gate can follow each other with variations in the ground potential power rail V.sub.EE.
A problem presented by this conventional TTL to ECL/CML translator circuit structure however is that the threshold voltage level, V.sub.TH or V.sub.TM REF is no longer temperature compensated. The circuit is therefore vulnerable to the disadvantages which are caused by variation in the threshold voltage level value applied at the base node of the reference transistor element with variations in the operating temperature, process variations, and V.sub.CC power rail variations.
Variation in the threshold voltage level V.sub.TH as a result of the conventional threshold clamp circuit diode stack illustrated in FIG. 1 may be analyzed as follows. The voltage drop V.sub.BE, also designated .phi., across the base/emitter junction of a bipolar transistor element is approximately 0.7v or 0.8v with a negative temperature coefficient or tempco of -1.6 mV/.degree. C. As a result of the negative temperature coefficient, the voltage drop across the base to emitter junctions of the BS transistor element diodes Q7 and Q8 decreases with increasing temperature. The typical voltage drop across the Schottky diode SD2 is 0.6v with a temperature coefficient or tempco of -1.4 mV/.degree. C. Again because of the negative temperature coefficient, the voltage drop across the Schottky diode decreases with increasing temperature. As a result of the cumulative fluctuations of the threshold clamp circuit with temperature, the threshold voltage level V.sub.TH with a value of 1.4v at room temperature may vary from 0.9v to 1.9v over temperature operating range specifications from -55.degree. C. to 125.degree. C. At least three disadvantages follow upon such a wide variation of the threshold voltage.
First as illustrated in FIG. 2, the wide variation in threshold voltage leaves only narrow noise margins in the range of for example, 300 mV to 500 mV for possible variations in the logic high and low signal potential levels V.sub.TH, V.sub.TL at the base node of the input transistor element. Variation of the input signals in excess of the narrow noise margins may cause false switching of the translator circuit ECL gate and false signals at the ECL output.
Second, the wide range of variation in the threshold voltage causes variation and inconsistency in the speed of transition of the translator circuit between the high and low potential levels. In particular there is increased skew or hysteresis in the propagation delay or time of propagation between the high to low propagation time tpHL and the propagation time for low to high transition tpLH. Undesirable skew is the time difference between tpLH and tpHL. The time of propagation is measured for example at the 1.5v crossover point and is the delay time between the 1.5v crossover point at the base node of the input transistor element of the translator circuit ECL gate and the 1.5v crossover point at the ECL output ECL OUT. In the case of the TTL to ECL/CML translator circuit, the crossover point is taken to be the threshold voltage level and the threshold voltage level variations therefore translate to variations in the propagation delay and increased skew.
Finally, variation in the threshold voltage level causes increased sensitivity to internal ground bounce. Because of the small noise margin a relatively small negative internal ground bounce may cause false data signals to occur, false clocking, or other glitches.